HBM evolution: from HBM3 to HBM4 and the AI memory war

Updated December 11, 2025

December 2025 Update: SK Hynix leading HBM with 62% Q2 2025 share vs Micron (21%) and Samsung (17%). Global HBM market growing from $38B (2025) to $58B (2026). JEDEC releasing official HBM4 spec (April 2025) doubling interface to 2,048 bits enabling 2TB/s per stack. SK Hynix overtaking Samsung as world's largest DRAM manufacturer for first time in history.

SK Hynix leads the HBM market with 62% share in Q2 2025, followed by Micron at 21% and Samsung at 17%.¹ The global HBM market will grow from $38 billion in 2025 to $58 billion in 2026.² JEDEC released the official HBM4 specification in April 2025, doubling the interface width to 2,048 bits and enabling up to 2 terabytes per second bandwidth per stack.³ High Bandwidth Memory defines the ceiling of AI accelerator performance—the memory wall that determines how large a model can be and how fast it can run.

The HBM generations represent a manufacturing and packaging triumph. Stacking DRAM dies vertically with through-silicon vias (TSVs) and connecting them via interposer to GPU or accelerator dies creates memory bandwidth impossible with traditional DRAM packaging. Each generation increases capacity, bandwidth, and stack height while vendors compete on yield, qualification speed, and customer relationships. The competition reshaped the memory industry, with SK Hynix overtaking Samsung as the world's largest DRAM manufacturer for the first time in history.

HBM3: the foundation of current AI

HBM3, introduced in 2022, established the memory bandwidth capabilities that enabled the current AI boom.⁴ The architecture doubled channel count from 8 to 16 compared to HBM2e, while data rates scaled to 6.4 gigabits per second.⁵

Four HBM3 stacks connected to a processor via an interface running at 6.4 gigabits per second deliver over 3.2 terabytes per second of aggregate bandwidth.⁶ Individual stack bandwidth reaches approximately 819 gigabytes per second with an 8 GT/s 1024-bit bus.⁷

HBM3 supports 16-high stacks of 32 gigabit capacity DRAM dies.⁸ The stacking capability enables memory capacities reaching 24-36 gigabytes per stack depending on die density and stack height.⁹

The 3D stacking architecture reduces latency compared to traditional DRAM through shorter signal paths and parallel access to multiple dies simultaneously.¹⁰ The combination of bandwidth, capacity, and latency improvements made HBM3 the memory technology that enabled transformer-based large language models at scale.

NVIDIA's H100 GPU used HBM3, establishing the performance baseline that competitors targeted. The memory bandwidth enabled the tensor core utilization rates that justified H100's price premium over previous generations.

HBM3E: pushing the limits

Major DRAM manufacturers introduced HBM3E devices pushing data rates to 9.6 gigabits per second—50% faster than HBM3.¹¹ The bandwidth improvement enabled approximately 1.2 terabytes per second per stack, approaching the practical limits of the 1024-bit interface.¹²

SK Hynix leads mass production with 12-high die stacks delivering 1.2+ terabytes per second bandwidth while remaining backward compatible with HBM3 controllers.¹³ The backward compatibility simplified adoption for accelerator vendors updating memory specifications between product generations.

Micron announced HBM3E memory with 9.6 gigabits per second per pin processing speed, 24 gigabytes per 8-high cube, and data transfer at 1.2 terabytes per second.¹⁴ The capacity per stack increased while maintaining the existing interface width.

Cadence demonstrated HBM3E memory subsystems running at 12.4 gigabits per second at nominal voltages, with production PHY supporting DRAM speeds up to 10.4 gigabits per second—1.33 terabytes per second per device.¹⁵ The demonstration showed headroom for even higher speeds within the HBM3E specification.

NVIDIA's H200 and initial Blackwell products use HBM3E. The H200 expanded memory capacity to 141 gigabytes compared to H100's 80 gigabytes while increasing bandwidth proportionally. The Blackwell B200 reached 192 gigabytes of HBM3E at 8 terabytes per second aggregate bandwidth.

The transition from HBM3 to HBM3E demonstrated the memory industry's ability to extract additional performance from existing architectures. However, further gains require the architectural changes that HBM4 introduces.

HBM4: the next generation

JEDEC released the official HBM4 specification in April 2025.¹⁶ The specification represents the most significant architectural change since HBM's introduction, doubling the interface width from 1,024 bits to 2,048 bits.¹⁷

HBM4 supports transfer speeds up to 8 gigabits per second across the wider interface, with total bandwidth reaching 2 terabytes per second per stack.¹⁸ A GPU with 8 HBM4 devices achieves aggregate memory bandwidth over 13 terabytes per second.¹⁹

The wider interface required architectural changes throughout the memory subsystem. HBM4 doubles the number of independent channels per stack to 32 with 2 pseudo-channels per channel.²⁰ The 2,048-bit data channel divides into 32 64-bit channels or 64 32-bit pseudo-channels, compared to HBM3's 16 64-bit channels.²¹

Stack height increases to 16 dies maximum with DRAM die densities of 24 gigabits or 32 gigabits, enabling capacities up to 64 gigabytes per stack.²² The capacity increase addresses the growing parameter counts of foundation models that exceed current memory limits.

HBM4 maintains backward compatibility with HBM3 controllers, easing the transition for accelerator vendors.²³ The Rambus HBM4 Memory Controller raises supported signaling speed to 10.0 gigabits per second, providing 2.56 terabytes per second throughput per HBM4 device at maximum rate.²⁴

Reliability improvements include Directed Refresh Management (DRFM) for improved row-hammer mitigation.²⁵ The enhanced RAS (Reliability, Availability, Serviceability) features address concerns about DRAM reliability at the elevated temperatures common in AI accelerators.

HBM4E extends the specification further with 10 gigabits per second data rates, 2.5 terabytes per second bandwidth per stack, and per-package power up to 80 watts.²⁶ The HBM4E specification targets the 2027 timeframe.

Manufacturer competition

SK Hynix completed HBM4 development and prepared for high-volume manufacturing by late 2025.²⁷ SK Hynix's HBM4 stacks exceed JEDEC specifications by 25% in performance, featuring 10 GT/s data transfer rates compared to the 8 GT/s standard.²⁸ Volume shipments begin in early 2026 after final customer qualifications.²⁹

SK Hynix became NVIDIA's primary HBM supplier, a relationship that drove the company's market share gains.³⁰ The NVIDIA partnership positioned SK Hynix to capture the majority of high-value AI memory demand.

Micron began shipping HBM4 samples in June 2025, providing 36 gigabyte 12-high stacks to key customers including reportedly NVIDIA.³¹ By Q4 2025, Micron announced HBM4 samples running at speeds above 11 gigabits per second per pin, delivering over 2.8 terabytes per second per stack.³² Mass production timing targets calendar 2026.³³

Micron secured design wins with NVIDIA for Hopper H200 and Blackwell B200 GPUs, growing HBM market share from approximately 5% toward a 20-25% target by end of 2025.³⁴ The NVIDIA qualification validates Micron's technology and manufacturing capability.

Samsung aims to start HBM4 mass production in the first half of 2026.³⁵ In Q3 2025, Samsung began shipping large volumes of HBM4 samples to NVIDIA for early qualification.³⁶ Samsung reportedly serves as the primary HBM4 supplier for AMD's MI450 accelerator.³⁷

Samsung's HBM market share plummeted from 41% in Q2 2024 to 17% in Q2 2025 as the company struggled to pass NVIDIA's qualification tests.³⁸ Samsung remained largely dependent on older-generation HBM3 chips for HBM sales while competitors shipped HBM3E.³⁹ Analysts forecast Samsung's position will strengthen as HBM3E parts qualify and HBM4 enters full-scale supply in 2026.⁴⁰

The HBM competition reshaped the broader memory industry. SK Hynix took the lead for the first time in the overall DRAM market, grabbing 36% share of revenues in Q1 2025 compared to Samsung's 34%.⁴¹ The reversal of the long-standing Samsung leadership reflects HBM's growing share of total DRAM value.

NVIDIA and AMD roadmaps

NVIDIA's official roadmap shows Rubin with 8 HBM4 sites and Rubin Ultra with 16 HBM4 sites.⁴² The Rubin interposer measures 2,194 square millimeters and hosts 288 to 384 gigabytes of VRAM capacity with 16-32 terabytes per second total bandwidth.⁴³ Total chip power reaches 2,200 watts.⁴⁴

HBM capacity projects to grow from the A100's 80 gigabytes of HBM2E to 1,024 gigabytes of HBM4E for Rubin Ultra.⁴⁵ The trajectory reflects the memory requirements of models that may reach tens of trillions of parameters.

Rubin production is on track for the second half of 2026.⁴⁶ Consumer cards based on the architecture are expected in late 2026 or early 2027.⁴⁷ The timing positions Rubin as the successor to Blackwell Ultra in NVIDIA's data center lineup.

AMD confirmed HBM4 for the MI400 accelerator series.⁴⁸ AMD's Instinct MI400, launching in 2026, targets 432 gigabytes of HBM4 capacity with memory bandwidth up to 19.6 terabytes per second.⁴⁹ The MI430X is the first AMD accelerator to utilize HBM4.⁵⁰

The HBM4 generation establishes a new performance tier for both vendors. Memory bandwidth and capacity increases enable model sizes and inference throughput that HBM3E cannot support efficiently.

The memory wall constraint

Memory bandwidth growth lags compute capability growth in AI accelerators. The "memory wall" constrains how effectively accelerators utilize their computational resources. HBM evolution represents the industry's primary response to this constraint.

Large language models exhibit memory-bound characteristics during inference. The attention mechanism requires accessing the full key-value cache for each generated token. Memory bandwidth determines how quickly this access occurs, directly affecting tokens-per-second throughput.

Training workloads face different memory constraints. Model parameters, gradients, optimizer states, and activations compete for memory capacity. Memory bandwidth affects how quickly data moves between processing units during gradient accumulation and optimization steps.

The 2 terabytes per second bandwidth of HBM4 compared to HBM3's 819 gigabytes per second represents a 2.4x improvement.⁵¹ Combined with capacity increases from 36 gigabytes to 64 gigabytes per stack, HBM4 addresses both bandwidth and capacity dimensions of the memory wall.

However, compute capability increases faster than memory bandwidth. Each HBM generation provides approximately 2x bandwidth improvement while compute doubles every generation as well. The memory wall recedes but never disappears.

Future HBM generations—HBM5 through HBM8—project continued bandwidth scaling through higher data rates and potentially wider interfaces.⁵² The roadmap extends through the decade with bandwidth targets reaching 64 terabytes per second per system.⁵³

Infrastructure planning considerations

HBM supply constraints affect accelerator availability. The HBM shortage limited GPU shipments throughout 2023 and 2024. Organizations planning large deployments should understand that GPU procurement depends on memory manufacturer capacity.

Vendor relationships determine access. SK Hynix's NVIDIA relationship, Samsung's AMD positioning, and Micron's broad qualification efforts create supply chain complexity. Second-tier accelerator vendors may face longer lead times if memory prioritizes hyperscaler orders.

The HBM4 transition creates a generational shift in late 2026. Organizations deploying now receive HBM3E-based systems. Those waiting for Rubin or MI400 gain HBM4's advantages. The timing affects multi-year infrastructure planning.

Memory determines accelerator value. An H200's 141 gigabytes of HBM3E enables workloads that an H100's 80 gigabytes cannot support efficiently. The memory configuration often matters more than raw compute for inference-dominant deployments.

Testing and qualification cycles affect availability. NVIDIA's qualification rigor limits which memory passes. Samsung's HBM3E qualification delays cost market share. Organizations should factor qualification uncertainty into deployment timelines.

The HBM market's trajectory from HBM3 to HBM4 reflects AI's memory demands reshaping the semiconductor industry. SK Hynix's displacement of Samsung as memory leader, Micron's growth from single-digit share, and the $58 billion 2026 market projection all trace to AI accelerator memory requirements. The memory wall remains the binding constraint on AI infrastructure performance, and HBM evolution remains the primary response.

Key takeaways

For infrastructure planners: - HBM4: 2,048-bit interface (2x HBM3), 2TB/s per stack, 64GB capacity - NVIDIA Rubin: 288-384GB VRAM, 16-32TB/s bandwidth, 2,200W power - HBM supply constraints directly affect GPU availability—memory determines accelerator value

For procurement teams: - Market share Q2 2025: SK Hynix 62%, Micron 21%, Samsung 17% - Global HBM market: $38B (2025) → $58B (2026) - Samsung fell from 41% to 17% due to NVIDIA qualification struggles

For capacity planning: - HBM4 production: SK Hynix/Samsung H1 2026, Micron calendar 2026 - NVIDIA Rubin timing: H2 2026 (production), late 2026/early 2027 (consumer) - AMD MI400: 432GB HBM4 capacity, 19.6TB/s bandwidth (2026)

For technology strategy: - Memory bandwidth (2TB/s HBM4 vs 819GB/s HBM3) is 2.4x improvement - Memory wall persists—compute doubles each generation but so does memory bandwidth - HBM5-HBM8 roadmap targets 64TB/s per system bandwidth through the decade

References

1. Astute Group. "SK hynix holds 62% of HBM, Micron overtakes Samsung, 2026 battle pivots to HBM4." 2025. https://www.astutegroup.com/news/general/sk-hynix-holds-62-of-hbm-micron-overtakes-samsung-2026-battle-pivots-to-hbm4/

2. Astute Group. "SK hynix holds 62% of HBM."

3. Wikipedia. "High Bandwidth Memory." 2025. https://en.wikipedia.org/wiki/High_Bandwidth_Memory

4. Rambus. "High Bandwidth Memory (HBM): Everything You Need to Know." 2024. https://www.rambus.com/blogs/hbm3-everything-you-need-to-know/

5. Wevolver. "What is High Bandwidth Memory 3 (HBM3): Complete Engineering Guide 2025." 2025. https://www.wevolver.com/article/what-is-high-bandwidth-memory-3-hbm3-complete-engineering-guide-2025

6. Rambus. "High Bandwidth Memory (HBM)."

7. Wikipedia. "High Bandwidth Memory."

8. Rambus. "High Bandwidth Memory (HBM)."

9. Wikipedia. "High Bandwidth Memory."

10. Wevolver. "What is High Bandwidth Memory 3 (HBM3)."

11. Semi Engineering. "HBM3E: All About Bandwidth." 2024. https://semiengineering.com/hbm3e-all-about-bandwidth/

12. Semi Engineering. "HBM3E: All About Bandwidth."

13. Semi Engineering. "HBM3E: All About Bandwidth."

14. Wevolver. "High Bandwidth Memory: Concepts, Architecture, and Applications." 2024. https://www.wevolver.com/article/high-bandwidth-memory

15. Semi Engineering. "HBM3E: All About Bandwidth."

16. Wikipedia. "High Bandwidth Memory."

17. Rambus. "Breakthrough to Greater Bandwidth with HBM4 Memory." October 2025. https://www.chipestimate.com/Breakthrough-to-Greater-Bandwidth-with-HBM4-Memory/Rambus/Technical-Article/2025/10/28

18. Wikipedia. "High Bandwidth Memory."

19. Semi Engineering. "HBM4 Feeds Generative AI's Hunger For More Memory Bandwidth." 2025. https://semiengineering.com/hbm4-feeds-generative-ais-hunger-for-more-memory-bandwidth/

20. Wikipedia. "High Bandwidth Memory."

21. Rambus. "Breakthrough to Greater Bandwidth with HBM4 Memory."

22. Wikipedia. "High Bandwidth Memory."

23. Wikipedia. "High Bandwidth Memory."

24. Rambus. "Breakthrough to Greater Bandwidth with HBM4 Memory."

25. Wikipedia. "High Bandwidth Memory."

26. SemiAnalysis. "Scaling the Memory Wall: The Rise and Roadmap of HBM." 2025. https://newsletter.semianalysis.com/p/scaling-the-memory-wall-the-rise-and-roadmap-of-hbm

27. Tom's Hardware. "SK hynix completes development of next-gen HBM4 — 2,048-bit interface and 10 GT/s speeds promised for next-gen AI accelerators." 2025. https://www.tomshardware.com/pc-components/dram/sk-hynix-completes-development-of-hbm4-2-048-bit-interface-and-10-gt-s-speeds-promised

28. Tom's Hardware. "SK hynix completes development of next-gen HBM4."

29. Tom's Hardware. "SK hynix completes development of next-gen HBM4."

30. Tom's Hardware. "SK hynix dethrones Samsung to become world's top-selling memory maker for the first time — success mostly attributed to its HBM3 dominance for Nvidia's AI GPUs." 2025. https://www.tomshardware.com/tech-industry/sk-hynix-dethrones-samsung-to-become-worlds-top-selling-memory-maker-for-the-first-time-success-mostly-attributed-to-its-hbm3-dominance-for-nvidias-ai-gpus

31. Tom's Hardware. "HBM roadmaps for Micron, Samsung, and SK hynix: To HBM4 and beyond." 2025. https://www.tomshardware.com/tech-industry/semiconductors/hbm-roadmaps-for-micron-samsung-and-sk-hynix-to-hbm4-and-beyond

32. Tom's Hardware. "HBM roadmaps for Micron, Samsung, and SK hynix."

33. Tom's Hardware. "HBM roadmaps for Micron, Samsung, and SK hynix."

34. Mark Lapedus Substack. "SK Hynix, Micron Gain Share In HBM But Samsung Loses Ground." 2025. https://marklapedus.substack.com/p/sk-hynix-micron-gain-share-in-hbm

35. TechPowerUp. "Samsung HBM4 Development Complete, Mass Production Pending NVIDIA Approval." 2025. https://www.techpowerup.com/343595/samsung-hbm4-development-complete-mass-production-pending-nvidia-approval

36. TechPowerUp. "Samsung HBM4 Development Complete."

37. Tom's Hardware. "HBM roadmaps for Micron, Samsung, and SK hynix."

38. Astute Group. "SK hynix holds 62% of HBM."

39. Mark Lapedus Substack. "SK Hynix, Micron Gain Share In HBM."

40. Mark Lapedus Substack. "SK Hynix, Micron Gain Share In HBM."

41. Mark Lapedus Substack. "SK Hynix Surpasses Samsung in DRAM Share." 2025. https://marklapedus.substack.com/p/sk-hynix-surpasses-samsung-in-dram

42. TSPA Semiconductor Substack. "The Infinite AI Compute Loop: HBM Big Three + TSMC × NVIDIA × OpenAI Shaping the Next-Generation Industry Chain." 2025. https://tspasemiconductor.substack.com/p/the-infinite-ai-compute-loop-hbm

43. Tom's Hardware. "Desktop GPU roadmap: Nvidia Rubin, AMD UDNA & Intel Xe3 Celestial." 2025. https://www.tomshardware.com/pc-components/gpus/desktop-gpu-roadmap-nvidia-rubin-amd-udna-and-intel-xe3-celestial

44. Tom's Hardware. "Desktop GPU roadmap."

45. SemiAnalysis. "Scaling the Memory Wall."

46. CNBC. "Nvidia-supplier SK Hynix readies production for cutting-edge HBM4 memory chips." September 2025. https://www.cnbc.com/2025/09/12/sk-hynix-hbm4-chips-nvidia-samsung-micron.html

47. Tom's Hardware. "Desktop GPU roadmap."

48. WCCFTech. "Next-Gen HBM Architecture Detailed Including HBM4, HBM5, HBM6, HBM7 & HBM8." 2025. https://wccftech.com/next-gen-hbm-architecture-detailed-hbm4-hbm5-hbm6-hbm7-hbm8-up-to-64-tbps-bandwidth-240-gb-capacity-per-24-hi-stack-embedded-cooling/

49. WCCFTech. "Next-Gen HBM Architecture Detailed."

50. WCCFTech. "Next-Gen HBM Architecture Detailed."

51. Rambus. "Breakthrough to Greater Bandwidth with HBM4 Memory."

52. WCCFTech. "Next-Gen HBM Architecture Detailed."

53. WCCFTech. "Next-Gen HBM Architecture Detailed."

SEO Elements

Squarespace Excerpt (159 characters): SK Hynix leads HBM with 62% share. HBM4 doubles interface to 2TB/s bandwidth. Samsung falls to 17%. The $58B memory war reshaping AI accelerator supply chains.

SEO Title (55 characters): HBM Evolution: HBM3 to HBM4 and the AI Memory War 2025

SEO Description (155 characters): HBM4 specification: 2048-bit interface, 2TB/s bandwidth, 64GB capacity. SK Hynix 62% share vs Samsung 17%. Analysis of high bandwidth memory for AI GPUs.

URL Slugs: - Primary: hbm-evolution-hbm3-hbm3e-hbm4-memory-ai-gpu - Alt 1: sk-hynix-samsung-micron-hbm-market-share-2025 - Alt 2: hbm4-specifications-nvidia-rubin-amd-mi400 - Alt 3: high-bandwidth-memory-ai-accelerator-gpu-roadmap